Embedded.com just ran a nice story about debugging serial busses in FPGAs: http://tinyurl.com/kltw7y

I agree with the article but cannot always afford the luxury of a new high end scope to capture the serial stream for easy debugging and instead rely on the FPGA vendor supplied logic analysis tools (Altera / Signal Tap) by adding a simple shift register to capture bytes or if the serial stream is slow speed, adding an LSF core called “Monitor” that captures the serial data internally and streams byte values in ASCII through a UART to a serial port.

Coupling that to a terminal program (Hyperterm or Tera term) allows you to capture and log the data being streamed in the chip. Check the downloads page here shortly for the release of the monitor code. I plan on making it freely available.