EDN has a good article on code coverage (see link below) - There is of course, no one definitive way to ensure your RTL is being verified 100% but by using a combination of static code coverage tools, assertions and (in the case of making an ASIC) prototyping in FPGA’s to ensure functionality, you can close to near 100%.

The article points out that System Verilog now has assertions built in, something VHDL has had for years and that more and more designers are including them in their code, as they should. The article does not touch on re-use at all. Code re-use can save both development and verification time. Building up a library of often used interfaces and code blocks allows a team to trust both the RTL and DV code bases.

Read the article here:

http://www.edn.com/article/CA6619018.html

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Tags: Assertions, DV, Verilog, VHDL

This entry was posted on Friday, December 19th, 2008 at 3:26 pm and is filed under RTL. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.